1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. In particular, the present invention relates to a method of manufacturing a salicide layer in an embedded structure.
2. Description of the Related Art
Typically, logic devices and memory devices are formed on the different wafers. In order to increase the efficiency of the integrated circuits (ICs), an embedded structure comprising a memory device region and a logic circuit region has been developed. The embedded structure has the benefit of decreasing production cost as well as improving the functional capacity of the devices. Integration improves functionality by lowering the time delay for sending signals from a memory device in one part of a semiconductor chip to a logic device in another part of another semiconductor chip. In addition, by putting memory and logic devices together on a semiconductor chip, cost of production is lowered because they can share most common fabrication procedures.
The most common embedded structure is an embedded dynamic random access memory (DRAM). The embedded DRAM comprises a logic circuit, a transfer field effect transistor (transfer FET) and a capacitor electrically coupled to the transfer FET. The transfer FET is used as a selectively coupled switch between a bottom electrode of the capacitor and a bit line. Hence, the data can be read from or stored in the capacitor.
FIGS. 1A through 1D are schematic, cross-sectional views of the conventional process for manufacturing a salicide layer in an embedded structure.
As shown in FIG. 1A, a substrate 100 having a memory region 102a and a logic circuit region 102b, which are isolated by an isolation region (not shown), is provided. A gate oxide layer 104 is formed over the substrate 100. A polysilicon layer 106 and a silicide layer 108 are formed over the substrate 100 in sequence.
As shown in FIG. 1B, the silicide layer 108, the polysilicon layer 106 and the gate oxide layer 104 are patterned to form gate oxide layers 104a and 104b, polysilicon layers 106a and 106b and silicide layers 108a and 108b. The gate oxide layer 104a, the polysilicon layer 106a and the silicide layer 108a together form a gate structure 110a. The gate oxide layer 104b, the polysilicon layer 106b and the silicide layer 108b together form a gate structure 110b. Source/drain regions 112a and 112b are formed in the substrate 100 by an implantation step and spacers 114a and 114b are respectively formed on the sidewalls of the gate structures 110a and 110b.
As shown in FIG. 1C, an oxide layer 116 is formed to cover the memory region 102a. A titanium layer 118 is formed over the substrate 100.
As shown in FIG. 1D, a portion of the titanium layer 118 over the source/drain region 112b is silicified by a thermal process to form a salicide layer 120. The remaining titanium layer 118 and the oxide layer 116 (as shown in FIG. 1C) are removed.
Conventionally, the silicide layers 108a and 108b formed on the polysilicon layers 106a and 106b are used to decrease the resistance of the gate structure. However, the implantation step used to form the source/drain regions 112a and 112b affects the structure of the silicide layers 108a and 108b while the implantation step is performed. Additionally, the annealing step used to uniform the ion distribution in the source/drain regions 112a and 112b and to decrease the stress of the source/drain regions 112a and 112b also affects the structure of the silicide layers 108a and 108b. Therefore, the resistance of the gate structure cannot be efficiently reduced and the reliability of the devices is poor.
The contact resistance of the gate structure and the source/drain can be efficiently reduced by forming the salicide layer on the gate structure and the source/drain. In the view of the logic circuit device, the operation rate can be increased by forming the salicide layer. But in the view of the memory device, the shallow junction of the source/drain region becomes thinner as the salicide layer is formed on the source/drain region, and thus serious leakage occurs at the capacitor electrically coupled to the source/drain region in the memory device.